The present invention relates to an information processor in which an arithmetic control unit (ACU), a main memory unit (MMU), and an input and output controller are subject to firmware control and, more particularly, to the above type information processor in which an interrupt from each of the units is acceptable even during the execution of instructions of the firmware.
With the recent development of large scale integration (LSI), it is a common practice that the arithmetic control part and the input/output control part in a microcomputer system are constructed by hardwired logic. The need of cost reduction and easy alternation of the system function has developed a computer system using soft logic called firmware now predominantly used in various types of information processors. The firmware, comprised of a number of microinstructions, is loaded in a read only memory (ROM) and microinstructions (several or several tens of steps) corresponding to a mnemonic written by a user are read out and executed. The firmware includes instructions for accessing a bus such as a COM instruction and an instruction for inhibiting an interrupt, e.g., a JUMP instruction.
Referring now to FIG. 1, there is shown an interconnection among the respective units forming an information processor. As shown, a main memory unit (MMU) 1 is connected through a memory bus (M-BUS) 2 to a central processing unit (CPU) 3. A plurality of input/output units (I/O(l) to I/O(n)) are connected to CPU 3, through an input/output bus 5. CPU 3 is provided with an input and output device controller (IOC) 6. With this constructed information processor, when receiving an instruction from CPU 3, a input/output unit 4 produces an interrupt request signal to CPU 3 to request a data transfer to and from MMU 1. In such a data transfer, the address of MMU 1 and the transfer block length of the data to be transferred, etc. are controlled by CPU 3.
When the data transfer is completed or an error takes place during the data transfer, the input/output unit 4 produces an interrrupt signal toward CPU 3 for terminating the data transfer. The data transfer in such a case is carried out in the following manner. The I/O unit 4 sends an interrupt request signal to the I/O bus 5 and CPU 3 receives the interrupt request signal and produces an interrupt acknowledge signal. The interrupt acknowledge signal passes through respective input/output units (I/O(l) to I/O(n)) to reach the I/O unit 4 which has produced the interrupt signal. This interrupt acknowledging method is called a daisy chain system. Upon receipt of the interrupt acknowledge signal, the I/O unit 4 issues the interrupt signal information necessary for the I/O bus 5 such as a channel number and a kind of interruption. When the kind of interrupt is a data transfer request, CPU 3 accesses the main memory 1 and performs a data transfer with the I/O unit 4.
FIG. 2 shows an interconnection of another information processor for which the invention is applied. In this system, an arithmetic control unit (ACU) 12, input/output controllers (IOC(l) to IOC(n)) 14 and a main memory unit (MMU) 13 are commonly connected to a common bus 11. CPU 3 in this case is provided with a plurality of IOCs which control various input and output devices (I/O devices). With such a construction, the respective units, i.e. ACU 12, IOC 14 and MMU 13, may be connected to the common bus 11. Each IOC 14 may be so designed as to supervise a plurality of IOCs or connect a plurality of ACUs 12 to the common bus 11. Thus constructed the processor can effect decentralized data processing and improve the throughput. The respective units 12 to 14, connected to the common bus 11, are each provided with a contention circuit for the bus 11. When the bus 11 is used, a bus busy signal, the address (channel number) of a called opposite unit, the address (channel number) of a calling unit, transfer data, control information and like are outputted to the bus 11. The called opposite unit, when receiving the information, transmits or receives information in accordance with the control information to and from the calling unit. When the ACU 12 executes the bus access instruction in the firmware and (1) is going to issue a request for using the bus 11, (2) has issued the request, (3) is currently executing an interrupt inhibition instruction, or (4) interrupts the execution of the firmware, if another unit on the bus seizes the bus 11 and makes an access to the ACU 12, the interrupt can not be accepted until the ACU 12 completes the execution of the firmware and use of the bus.